Seminar on Harnessing the Power of SystemVerilog and Assertions

Harnessing the Power of SystemVerilog and Assertions Register to Attend: http://www.aldec.com/Events Date: Thursday, March 25, 2010 Time: 11:30am – 2:00pm PDT Location: Silicon Valley (exact location TBD and will be forwared to registrants) Presenter: Nasir Junejo Nasir Junejo is a 20+ year veteran of the EDA and Verification industry. He worked for Cadence Design Systems for 20 years as a Consultant, Educational Consultant, Instructor, and Application Engineer in both leadership […]