Case Study - Fabless Semiconductor Start-up (Turn-key Project)

 

Projects

• Design Highlights
• 0.13um TSMC ASIC Design
• 125 derived clocks, Max clock freq 256 MHz
• Activity
• Floorplan, TOP RTL Integration, DFT (MBIST, SCAN, JTAG), Synthesis, Block/Full-chip SDC Generation, Layout Timing Closure with STA, SDF Gate Sims, ATE Vector Generation and Debug
• Tools
• Cadence - First Encounter, RTL Compiler, Conformal LEC, NCVerilog
• LogicVision – MBIST, JTAG
• Synopsys - PrimeTime
• Team Size
• Three engineers, 8 mo duration