Seminar on Harnessing the Power of SystemVerilog and Assertions

Harnessing the Power of SystemVerilog and Assertions

Register to Attend:

Date: Thursday, March 25, 2010
Time: 11:30am – 2:00pm PDT

Location: Silicon Valley (exact location TBD and will be forwared to registrants)

Presenter: Nasir Junejo
Nasir Junejo is a 20+ year veteran of the EDA and Verification industry. He worked for Cadence Design Systems for 20 years as a Consultant, Educational Consultant, Instructor, and Application Engineer in both leadership and contributor roles.
Having worked with start-ups to fortune 500 companies, Nasir brings a bundle of experience and knowledge in Functional Verification. He is well versed with the challenges and benefits of adopting SystemVerilog OVM methodology and surrounding technologies such as Verification Planning and Management. Nasir teaches the following classes: SystemVerilog, SystemVerilog Assertions, OVM Methodology, SystemC, VHDL and Verification Management and Planning.

Seminar Abstract
With the complexity of contemporary designs, the verification effort consumes a substantial part of the overall development time. The magnitude of this effort has stirred interest in the Assertion Based Verification (ABV) – a methodology that promises to run the verification process a lot faster, more efficiently and with less labor. This seminar demonstrates the advantages of using SystemVerilog assertions for design verification.

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